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20 v, 4 a synchronou s step - down regulator with low - side driver data sheet adp2380 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or o ther rights of third parties that may result from its use. specifications subject to change without notice. no licen se is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.3 29.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features input voltage : 4.5 v to 20 v integrated 44 m? h igh -s ide m osfet 0.6 v 1% r eference v oltage o ver t emperature contin u ous o utput c urrent: 4 a programmable switching frequency: 250 khz to 1.4 mhz synchronizes to e xternal c lock: 2 50 khz to 1.4 mhz 18 0 o ut - of -p hase s ynchronization programmable uvlo power -g ood o utput external c ompensation internal s oft s tart with external adjustable option start up into a p recharged o utput supported by adisimpower design tool applications communication s i nfrastructure n etworking and s ervers industrial and i nstrumentation healthcare and m edical intermediate power rail c onversion dc - to - dc point of load a pplication typical applications circuit adp2380 09939-001 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r osc r top r bot c ss c in c out v out c bst c vreg l v in c c_ea c cp_ea r c_ea fet figure 1. 100 50 55 60 65 70 75 80 85 90 95 0 1.0 2.0 3.5 2.5 1.5 0.5 3.0 4.0 efficiency (%) output current (a) v out = 1.2v v out = 3.3v v out = 5v 09939-002 figure 2 . effi ciency vs . output current, v in = 12 v, f sw = 250 k hz general description the adp2380 is a current mode cont rol , synchronous , step - down , dc - to - dc regulator. it integrates a 44 m? high - side power mosfet and a lo w- side driver to provide a high efficiency solution. the adp2380 runs from an input voltage of 4.5 v to 20 v and can deliver 4 a of output current. the o utput vol tage can be adjust ed to 0.6 v to 90% of the input voltage. the switching frequency of the adp2380 can be programmed from 2 50 khz to 1.4 mhz or fixed at 29 0 khz or 540 khz. the synchronization function allows the switching frequency to be synchronized to an external clock to minimize system noise. external compensation and an adjustable soft start provide design flexibility. the power - good output provide s simple and reliable power sequencing. additional features include programmable undervoltage lockout (uvlo) , overvoltage protection ( ovp ), over current protection ( ocp ), and thermal shutdown (tsd) . the adp2380 operates over the ? 40 c to +125 c junction temperature range and is available in a 16 -lead tssop_ep package .
adp2380 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical applications circuit ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal information ................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 functional block diagram ............................................................ 12 theory of operation ...................................................................... 13 control scheme .......................................................................... 13 internal regulator (vreg) ....................................................... 13 bootstrap circuitry .................................................................... 13 low - side driver .......................................................................... 13 oscillator ..................................................................................... 13 synchronization .......................................................................... 13 enable and soft start .................................................................. 13 power good ................................................................................. 14 peak c urrent - limit and short - circuit protection ................. 14 overvoltage protection (ovp) ................................................. 14 undervoltage lockout (uvlo) ............................................... 14 thermal shutdown ..................................................................... 14 applications information .............................................................. 15 input capacitor selection .......................................................... 15 output voltage setting .............................................................. 15 voltage conversion limitations ............................................... 15 inductor se lection ...................................................................... 15 output capacitor selection ....................................................... 17 low - side power device selection ............................................ 17 programming input voltage uvlo ........................................ 18 compensation design ............................................................... 18 adisimpower design tool ....................................................... 19 design example .............................................................................. 20 output voltage setting .............................................................. 20 frequency setting ....................................................................... 20 inductor selection ...................................................................... 20 output capacitor selection ....................................................... 20 low - side mosfet selection ................................................... 21 compensation components ..................................................... 21 soft start time program ........................................................... 21 input capacitor selectio n .......................................................... 21 recommended external components ........................................ 22 circuit board layout recommendations ................................... 24 typical applications circuits ........................................................ 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revi sion history 12 /12 revision 0: initial version
data sheet adp2380 rev. 0 | page 3 of 28 specifications v in = 12 v, t j = ? 40 c to +125 c for minimum/ max imum specifications, and t a = 25c for typical specification s , unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit pvin pvin voltage range v pvin 4.5 20 v quiescent current i q no s witching 2 .2 2.8 3. 4 ma shutdown current i shdn en/ss = gnd 85 1 25 17 0 a pvin undervoltage lockout threshold pvin rising 4.3 4.5 v pvin falling 3.7 3.9 v fb fb regulation voltage v fb 0c < t j < 85c 0. 594 0. 6 0. 606 v ? 40 c < t j < + 125 c 0. 5 9 1 0. 6 0. 6 0 9 v fb bias current i fb 0.01 0.1 a error amplifier (ea) transc onductance g m 34 0 470 590 s ea source current i source 45 60 75 a ea sink current i sink 45 60 75 a i nternal r egulator (vreg) vreg vol tage v vreg v pvin = 12 v, i vreg = 50 ma 7. 7 8 8 .4 v dropout voltage v pvin = 12 v, i vreg = 50 ma 3 50 mv regulator current l imit 65 100 13 0 ma sw high - side on resistance 1 v bs t ? v sw = 5 v 44 70 m high - side peak current limit 4.8 7 9 a ne gative current - limit threshold voltage 2 20 mv sw min imum on time t min_on 120 1 55 ns sw min imum off time t min_off 195 280 ns low - side driver (ld) rising time 2 t r c dl = 2 .2 nf ; see figure 17 20 ns falling time 2 t f c dl = 2 .2 nf ; see figure 20 10 ns sourcing resistor 4 6.5 sinking resistor 2 4. 5 bst bootstrap voltage v boot 4. 7 5 5. 6 v oscillator (rt pin) switching frequency f sw rt pin connected to gnd 21 0 29 0 35 0 khz rt pin open 41 0 54 0 65 0 khz r osc = 100 k 4 40 500 56 0 khz switching frequ e ncy range f sw 25 0 1400 khz sync synchronization range 25 0 1400 k hz sync minimum pulse width 100 ns sync minimum off time 100 ns sync input high voltage 1.3 v sync input low voltage 0.4 v en/ss enable threshold 0.5 v internal soft start 16 00 clock cycles ss pin pull - up current i ss_up 2. 4 3. 2 3.6 a
adp2380 data sheet rev. 0 | page 4 of 28 parameter symbol test conditions/comments min typ max unit power good (pgood) pgood range fb rising threshold 95 % fb falling threshold 90 % pgood deglitch time pgood from low to high 1024 clock cycles pgood from high to low 16 clock cycles pgood leakage current v pgood = 5 v 0. 01 0. 1 a pgood output low voltage i pgood = 1 ma 125 185 mv uvlo rising threshold 1.2 1.2 4 v falling threshold 1.0 6 1.1 v thermal thermal shutdow n threshold 150 c thermal shutdown hysteresis 25 c 1 pin - to - pin measurement. 2 guaranteed by design.
data sheet adp2380 rev. 0 | page 5 of 28 absolute maximum ratings table 2 . parameter rating p vin, pgood ? 0.3 v to + 22 v sw ? 1 v to + 22 v bst v sw + 6 v uvlo, fb , en/ s s, comp, sync, rt ? 0.3 v to +6 v vreg, ld ? 0.3 v to +12 v pgnd to gnd ? 0.3 v to +0.3 v operating junction temperature range ? 40 c to +125 c storage temperature range ? 65c to +150c sol dering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise spec ified , all other voltages are referenced to gnd. thermal i nformation table 3 . thermal resistance package type ja unit 16- lead tssop_ep 39.48 c/w ja is specified for the worst - case conditions, that is , a devic e soldered in circ uit board (4 -l ayer, jedec s tandard board) for surface - mount packages. esd caution
adp2380 data sheet rev. 0 | page 6 of 28 pin configuration and function descripti ons top view (not to scale) 1 2 3 4 5 6 7 8 adp2380 16 15 14 13 12 11 10 9 pvin uvlo pgood en/ss sync rt pvin sw sw ld gnd com p fb pgnd vreg bst notes 1. the exposed pad should be soldered to a large external copper ground plane underneath the ic for thermal dissipation. 09939-003 figure 3. pin configuration (top view) table 4 . pin function descrip tions pin no. mne monic description 1, 2 pvin power input. connect pvin to the input power source and connect a bypass capacitor between this pin and pgnd. 3 uvlo underv oltage lockout pin. an e xternal resistor divider can be used to set the turn - on thresh old. 4 pgood p ower - good output (open drain). it is recommended that a pull - up resistor of 10 k t o 100 k b e connected to pgood. 5 rt frequency setting. connect a resistor between rt and gnd to program th e switching frequency between 25 0 khz and 1.4 mhz. if the rt pin is connected to gnd, the switching frequency is set to 290 khz. if the rt pin i s open, the switching frequency is set to 54 0 khz. 6 sync synchronization input. connect this pin to an external clock to synchronize th e switching frequency between 25 0 khz and 1.4 mhz (see the oscillator section and the synchronization section for details). 7 en/ss enable (en). when this pin voltage falls below 0.5 v, the regulator is disabled. soft start (ss). this pin can also be used to set the s oft s tart time. connect a capacitor from ss to gn d to program the slow soft start time. if this pin is open, the regulator is enabled and uses the internal soft start. 8 comp error amplifier output. connect an rc network from comp to fb. 9 fb feedback voltage sense input . connect this pin to a resisto r divider from v out . 10 gnd analog ground. connect this pin to the ground plane. 11 pgnd power ground. connect this pin to the source of the synchronous n - channel mosfet. 12 vreg internal 8 v regulator output. place a 1 f ceramic capacitor between thi s pin and gnd . 13 ld low -s ide g ate d river o utput. connect this pin to the gate of the synchronous n - mosfet. 14, 15 sw switch node output . connect this pin to the output inductor. 16 bst supply rail for the high - side gate drive. place a 0.1 f ceramic ca pacitor between sw and bst . 17 epad exposed pad. the expo sed pad should be soldered to a large external copper ground plane underneath the ic for thermal dissipation.
data sheet adp2380 rev. 0 | page 7 of 28 typical performance characteristics t a = 25 o c, v in = 12 v, v out = 3.3 v, l = 4.7 h, c out = 2 100 f, f sw = 500 khz, unless otherwise noted. 100 50 55 60 65 70 75 80 85 90 95 0 4.0 efficiency (%) output current (a) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-3r3m mosfet: fds6298 09939-004 1.0 2.0 3.5 2.5 1.5 0.5 3.0 figure 4 . efficiency at v in = 12 v, f sw = 500 khz 4.0 1.0 2.0 3.5 2.5 1.5 0.5 3.0 100 50 55 60 65 70 75 80 85 90 95 0 efficiency (%) output current (a) v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-4r7m mosfet: fds6298 09939-005 figure 5 . efficiency at v in = 18 v, f sw = 500 khz 90 100 1 10 120 130 140 150 160 4 6 8 10 12 14 16 18 20 shutdown current (a) input vo lt age (v) t j = ?40c t j = +25c t j = +125c 09939-009 figure 6. s hutdown current vs. v in 4.0 1.0 2.0 3.5 2.5 1.5 0.5 3.0 100 50 55 60 65 70 75 80 85 90 95 0 efficiency (%) output current (a) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-6r8m mosfet: fds6298 09939-007 figure 7 . efficiency at v in = 12 v, f sw = 250 khz 4.0 1.0 2.0 3.5 2.5 1.5 0.5 3.0 100 50 55 60 65 70 75 80 85 90 95 0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v inductor: fdve1040-1r5m mosfet: fds6298 09939-008 figure 8 . efficiency at v in = 5 v, f sw = 500 khz 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4 6 8 10 12 14 16 18 20 quiescent current (ma) input vo lt age (v) t j = ?40c t j = +25c t j = +125c 09939-006 figure 9 . quiescent current vs. v in
adp2380 data sheet rev. 0 | page 8 of 28 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ?40 ?20 0 20 40 60 80 100 120 pvin uvlo threshold (v) tempera ture (c) rising falling 09939-010 figure 10 . pvin uvlo threshold vs. temperature 2.8 2.9 3.0 3.1 3.2 3.3 ?40 ?20 0 20 40 60 80 100 120 ss pull-u p current (a) tempera ture (c) 09939-012 figure 11 . ss pin pull -u p current vs. temperature tempera ture (c) 470 480 490 500 510 520 530 ?40 ?20 0 20 40 60 80 100 120 frequenc y (khz) 09939-014 r osc = 100k ? figure 12 . frequency vs. temperature 1.00 1.05 1.10 1.15 1.20 1.25 1.30 ?40 ?20 0 20 40 60 80 100 120 uvlo pin threshold (v) tempera ture (c) rising falling 09939-0 11 figure 13 . uvlo pin threshold vs. temperature tempera ture (c) 594 596 598 600 602 604 606 ?40 ?20 0 20 40 60 80 100 120 feedback vo lt age (mv) 09939-013 figure 14 . fb voltage vs. temperature 7.6 7.7 7.8 7.9 8.0 8.1 8.2 8.3 8.4 vreg vo lt age (v) ?40 ?20 0 20 40 60 80 100 120 tempera ture (c) 09939-015 figure 15 . vreg voltage vs. temperature
data sheet adp2380 rev. 0 | page 9 of 28 20 30 40 50 60 70 mosfet resis t or (m?) ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09939-016 figure 16 . mosfet r dson vs. temperature ch2 5.00v ch1 5.00v m20.0ns a ch2 5.50v 1 2 t 50.00% sw ld 09939-017 figure 17 . low - side driver rising edge waveform, c dl = 2.2 nf ch2 10v ch4 2a ? ch1 10mv b w b w m2.00s a ch2 8.00v 4 2 1 t 50.20% v out (ac) i l sw 09939-018 figure 18 . working mode waveform 5.0 5.5 6.0 6.5 7.0 7.5 8.0 peak curren t -limit threshold (a) ?40 ?20 0 20 40 60 80 100 120 tempera ture (c) 09939-019 figure 19 . current - limit threshold vs. temperature ch2 5.00v ch1 5.00v m20.0ns a ch2 3.70v 1 2 t 40.00% sw ld 09939-020 figure 20 . low - side driver falling edge waveform, c dl = 2.2 nf ch2 5.00v ch4 2.00a ? ch1 2.00v ch3 5.00v m2.00ms a ch2 4.40v 1 3 2 4 t 60.40% en/ss pgood v out i out b w b w b w 09939-021 figure 21 . soft start with full load
adp2380 data sheet rev. 0 | page 10 of 28 ch2 5.00v ch4 2.00a ? ch1 2.00v ch3 5.00v m2.00ms a ch2 4.40v 1 3 2 4 t 60.40% en/ss pgood v out i l b w b w b w 09939-022 figure 22 . precharged output ch1 100mv m200s a ch4 2.96a 1 4 t 70.40% ch4 2.00a ? v out (ac) i out b w b w 09939-023 figure 23 . load transient response, 1 a to 4 a ch2 10.0v ch4 5.00a ? ch1 2.00v m4.00ms a ch1 1.32v 1 2 4 t 20.40% v out sw i l b w b w 09939-024 figu re 24 . output short entry ch2 10.0v m1.00s a ch2 7.40v 3 2 t 50.40% ch3 5.00v sync sw b w 09939-025 figure 25 . external synchronization ch 1 20 mv m1ms a ch 3 13.8v 1 2 3 t 30% ch 3 5v ? b w b w ch 2 10v b w 09939 - 02 6 v out (ac) v in sw figure 26 . line transient response, v in from 10 v to 1 6 v, i out = 4 a ch2 10.0v ch4 5.00a ? ch1 2.00v m4.00ms a ch1 1.96v 1 2 4 t 70.20% v out sw i l b w b w 09939-027 figure 27 . o utput short recovery
data sheet adp2380 rev. 0 | page 11 of 28 5 0 1 2 3 4 45 55 65 75 85 95 105 load current (a) ambient temperature (c) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 09939-028 figure 28 . load current vs . ambient temperature, v in = 12 v, f sw = 500 khz 5 0 1 2 3 4 45 55 75 65 85 95 105 load current (a) ambient temperature (c) v out = 1v v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 09939-029 figure 29 . load current vs . ambient temperature, v in = 12 v, f sw = 250 khz
adp2380 data sheet rev. 0 | page 12 of 28 functional block diagram adp2380 oscillator rt sync uvlo clk slope ramp control logic and mosfet driver with anticross protection pgood gnd uvlo slope ramp ld pgnd + ? + 0.6v i ss en/ss fb amp comp 0.7v 0.54v 1.2v ovp clk + ? + ? + ? i max hiccup mode cmp ocp + ? + ? sw nfet bst driver vreg driver boost regulator deglitch bias and driver regulator + ? a cs pvin vreg 320k? 125k? pvin neg a tive curren t -limit cm p + ? 09939-030 figure 30 . functional block diagram
data sheet adp2380 rev. 0 | page 13 of 28 theory of operation the adp2380 is a synchronous , step - down, dc -to- dc regulator. it uses curr ent mode architecture with an integrated high - side power switch and a low - side driver. it targets high performance applications that require high efficiency and design flexibility. the adp2380 can operate with an input voltage from 4.5 v to 20 v and regulate the output voltage down to 0. 6 v. additional features for design flexibility include programmable switching frequency, soft start, external compensation , and power - good pin. control scheme the adp2380 uses fixed frequency, peak current mode pwm control architecture. at the start of each oscillator cycle, the high - side n- mosfet is turned on, putting a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current thresh - old that turns off the high - side n - mosfet and turn s on the low - side n - mosfet. t his puts a negative voltage across the inductor, causing the inductor current to decrease. the low - side n- mosfet stays on for the rest of the cycle. internal regulator ( vreg) the internal regulator provides a stable supply for the internal circuits and pr o vides bias voltage for the low - side gate driver. placing a 1 f ceramic capacitor between vreg and gnd is recommended. the internal regulator also includes a current - limit circuit to protect the circuit if the maximum external load is added. bootstrap cir cuitry the adp2380 has integrated the boot regulator to provide the gate drive voltage for the high - side n - mosfet. it generates a 5 v bootstrap voltage between bs t and sw by differential sensing. it is recommended to place a 0.1 f, x7r or x5r ceramic capacitor between the bst pin and the sw pin. low- side driver the ld pin provides the gate driver for the low - side n - channel mosfet . internal circuitry monitors the e xternal mosfet to ensure break - before - make switching to prevent cross conduction. oscillator the adp2380 switching frequency is controlled by the rt pin. if the rt pin is connected to gnd, the switching frequency is set to 29 0 khz. if the rt pin is open, the switching frequency is set to 54 0 khz. a resistor connected from rt to gnd can program the switching frequency according to the following equation: 15]k[ 600,57 ] khz [ + = osc sw r f a 100 k resistor sets the frequency to 500 khz , and a 215 k resistor sets the frequency to 250 khz. figure 31 shows the typical relationship between f sw and r osc . 1400 1200 1000 800 600 400 200 0 20 60 100 140 180 220 260 300 switching frequency (khz) r osc n? 09939-031 figure 31 . switching frequency vs. r osc s ynchronization to synchronize the adp2380 , connect an external clock to the sync pin. the frequency of the external clock can be in the range of 2 50 khz to 1.4 mh z. during synchronization, the switching rising edge runs 180 out of phase with the external clock rising edge. when the adp2380 is being synchronized , connect a resistor from the rt pin to gnd to program the internal oscillator to run at 90% to 110% of the external synchronization clock. enable and soft star t when the voltage of the en/ss pin exceeds 0.5 v, t h e adp2380 starts operation. the adp2380 has an internal digital soft start . the internal soft start time can be calculated by using the following equation: ) ms ( ]khz[ 1600 _ sw intss f t = a s low soft start time can be programmed by the en/ss pin. place a capacitor between the en/ss pin and gnd. an internal current charge s this capacitor to establish the soft start ramp. the soft start time can be calculated by using the following equation: up ss ss ext ss i c t _ _ v6.0 = w here : c ss is the soft start capacitance . i ss_up is the soft start pull - up current (3. 2 a) . the internal error amplifier includes three positive inputs: the internal reference voltage, the internal digital soft start voltage , and the en/ss voltage. the error amplifier regulates the fb voltage to the lowest of the three voltages .
adp2380 data sheet rev. 0 | page 14 of 28 if the output voltage is charged prior to turn - on, the adp2380 prevents the low - side mosfet from turning on, which discharge s the output voltage until the soft start voltage exceed s the voltage on the fb pin. when the regulator is disabled or a current fault hap pens, the soft start capacitor is discharged , and the internal digital soft start is reset to 0 v. power good the p ower - good (pgood) pin is an active high, open -d rain output that requires a pull - up resistor . a logic high indicates that the voltage at the f b pin (and, therefore, the output voltage) is above 95 % of the reference voltage and there is a 1024 cycle waiting period before pgood is pulled high. a logic low indicates that the voltage at the fb pin is below 90 % of the reference voltage and there is a 16- cycle waiting period before pgood is pulled low. peak cu rrent - limit and short - circuit protection the adp2380 has a peak current - limit protection circuit to pr event current runaway. during soft start, the adp2380 uses frequency foldback to prevent output current runaway. the switching frequency is reduced according to t he voltage on the fb pin, which allows more time for the inductor to discharge. the correlation between the switching frequency and fb pin voltage is shown in table 5 . table 5 . switching frequency and fb pi n voltage fb pin voltage switching frequency v fb 0.4 v f sw 0.4 v > v fb 0.2 v f sw /2 v fb < 0.2 v f sw /4 for heavy load protection, the adp2380 uses hiccup mode for overcurrent protection. when the inductor peak current reaches th e current - limit value, the high - side mosfet turns off and the low - side driver turns on until the next cycle , while the over cur rent counter increments. if the over current counter reaches 10, or the fb pin voltage falls to 0. 4 v afte r the soft start, the regulat or enters hiccup mode. the high - side mosfet and low - side mosfet are both turned off. the regulator remains in this mode for 4096 clock cycles and then attempts to restart. if the current - limit fault is cleared, the regulator re sumes normal operation. otherwise, it reenters hiccup mode. the adp2380 also provides a sink current limit to prevent the low - side mosfet from sinking a large amo unt of current from the load . when the voltage across the low - side mosfet exceeds the sink current - limit threshold, which is typical ly 20 m v, t h e low - side mosfet turns off immediately for th e rest of this cycle. both high - side and low - side mosfets turn off until the next clock cycle. in some cases, the input voltage (pvin) ramp rate is too slow or the output capacitor is too large to support the setting regulation voltage during the soft start , causing the regulator to enter hiccup mode. to avoid such cases , use a resistor divider at the uvlo pin to program the uvlo input voltage, or use a longer soft start time. over v oltage protection (o vp) the adp2380 provides an overvoltage protection feature to protect the system against an output that short s to a higher voltage supply or the occurrence of a strong load transient . if the feedback voltage increases to 0.7 v, the internal high - side mosfet and low - side driver are tu rned off until the voltage at fb decreases to 0.63 v. at that time , the adp2380 resumes normal operation. under v oltage lockout (uvlo ) the uvlo pin enable threshol d is 1.2 v with 100 mv hysteresis. the adp2380 has an internal voltage divider that consists of two resistors from pvin to gnd, with 320 k for the high - side resistor and 125 k for the low - side resistor. an e xternal resistor divider from pvin to gnd can be used to override the internal resistor divider. thermal shutdown in the event that the adp2380 junction temperatures rise above 150 c, the thermal shutdown circuit turns off the regulator. extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. a 25 c hysteresis is included so that , when thermal shutdown occurs, the adp2380 do es not return to oper ation until the on - chip tempera ture drops below 12 5 c . upon recovery, soft start is initiated prior to normal operation.
data sheet adp2380 rev. 0 | page 15 of 28 applications information input capacitor sele ction the input decoupling capacitor is used to attenuate high frequency noise on the input. this capacitor should b e a ceramic capacitor in the range of 10 f to 47 f. place the capacitor close to the pvin pin. the loop compose d of this input capacitor, high - side nfet , and low - side nfet must be kept as small as possible. the voltage rating of the input capacitor must be greater than the maximum input voltage. the rms current rating of the input capacitor should be larger than the following equation: )1( _ ddii out rms c in ?= output voltage setti ng the output voltage of adp2380 can be set by an external resistive divider using the following equation: ? ? ? ? ? ? ? ? += bot top out r r v 16.0 to limit output voltage accuracy degradation due to fb bias current (0.1 a maximum) to less than 0.5% (maximu m), ensure that r bot is less than 30 k?. table 6 list s the recommended resistor divider values for various output voltage options. table 6. resistor divider for different output voltage s v out (v) r top , 1 % (k?) r bot , 1% (k?) 1.0 10 15 1.2 10 10 1.5 15 10 1.8 20 10 2.5 47.5 15 3.3 10 2.21 5.0 22 3 voltage conversion l imitations the minimum output voltage for a given input voltage and switching frequency is constrained by the mini mum on time. the minimum on time of the adp2380 is typically 1 2 0 ns. the minimum output voltage at a given input voltage and frequency can be calculated using the following equation: v out_min = v in t min_on f sw ? ( r dson_hs ? r dson_ls ) i out_min t min_on f sw ? ( r dson_ls + r l ) i out_min (1) where: v out_min is the minimum output voltage. t min_on is the minimum on time. f sw is the switching frequency. r dson_hs is the high - side mosfet on resistance. r dson_ls is the low - side mosfet on resistance. i out_min is the minimum output current. r l is the series resistance of the output inductor. the maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and the maxim um duty cycle. the minimum off time is typically 20 0 ns , and the maximum duty cycle of the adp2380 is typically 90%. the maximum output voltage limited by the mi nimum off time at a given input voltage and frequency can be calculated using the following equation: v out_max = v in (1 ? t min_off f sw ) ? ( r dson_hs ? r dson_ls ) i out_max (1 ? t min_off f sw ) ? ( r dson_ls + r l ) i out_max (2) where: v out_max is the ma ximum output voltage. t min_off is the minimum off time. i out_max is the maximum output current. the maximum output voltage , limited by the maximum duty cycle at a given input voltage , can be calculated by using the following equation: v out_max = d max v in (3) where d max is the maximum duty. as equation 1 to equation 3 show, reducing the switching frequency alleviates the minimum on time and minimum off time limitation. inductor selection the inductor value is determined by the operating frequency, input vo ltage, output voltage, and inductor ripple current. using a small inductor leads to a faster transient response but degrades efficiency , due to larger inductor ripple current; whereas , using a large inductor value leads to smaller ripple current and better efficiency but results in a slower transient response. as a guideline, the inductor ripple current, i l , is typically set to 1/3 of the maximum load current. the inductor can be calculated using the following equation: ( ) d fi vv l sw l out in ? ? = where: v in is the input voltage. v out is the output voltage. i l is the in ductor current ripple. f sw is the switching frequency. d is the duty cycle. in out v v d = the adp2380 uses adaptive slope compensation in the current loo p to prevent sub harmonic oscillations when the duty cycle is larger than 50%. the internal slope compensation limits the minimum inductor value.
adp2380 data sheet rev. 0 | page 16 of 28 for a duty cycle that is larger than 50%, the minimum inductor value is determined by the following equation: l (minimum) = sw out f d v ? 2 )1( the inductor peak current is calculated using the following equation: i peak = i out + 2 l i ? the saturation current of the i nductor must be larger than the peak inductor current. for the ferrite core indu ctors with a quick saturation characteristic, the saturation current rating of the inductor must be higher than the current - limit threshold of the switch to prevent the inductor from becoming saturated . the rms current of the inductor can be calculated by 12 2 2 l out rms i ii ? += shielded f errite core materials are recommended for low core loss and low emi. table 7 lists some recommended inductors. table 7 . recommended inductors vendor part no. value i sat a i rms a dcr m toko fdve1040 - 1r5m 1.5 13.7 14.6 4.6 fdve1040 - 2r2m 2.2 11.4 11.6 6.8 fdve1040 - 3r3m 3.3 9.8 9.0 10.1 fdve1040 - 4r7m 4.7 8.2 8.0 13.8 fdve1040 - 6r8m 6.8 7.1 7.1 20.2 fdve1040 - 100m 10 6.1 5.2 34.1 vishay ihlp4040dz - 1r0m -01 1.0 36 17.5 4.1 ihlp 4040dz - 1r5m -01 1.5 27.5 15 5.8 ihlp4040dz - 2r2m -01 2.2 25.6 12 9 ihlp4040dz - 3r3m -01 3.3 18.6 10 14.4 ihlp4040dz - 4r7m -01 4.7 17 9.5 16.5 ihlp4040dz - 6r8m -01 6.8 13.5 8.0 23.3 ihlp4040dz - 100m -01 10 12 6.8 36.5 w rth elektronik 744 325 120 1.2 25 20 1.8 744 325 180 1.8 18 16 3.5 744 325 240 2.4 17 14 4.75 744 325 330 3.3 15 12 5.9 744 325 420 4.2 14 11 7.1 744 325 550 5.5 12 10 10.3
data sheet adp2380 rev. 0 | page 17 of 28 output capacitor sel ection the output capacitor selection affects both the output ripple voltage and the loop dynamics of the regulator. during a load step transient on the output, for example , when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp up the inductor current, which causes the outp ut to undershoot. the output capacitance required to satisfy the voltage droop requirement can be calculated using the following equation: ( ) uvout out in step uv uvout vvv lik c _ 2 _ 2 ?? ? = w here: k uv is a factor typically of 2. i step is the load step. v out_uv is the allowable undershoot on the output voltage. another case occurs when a lo ad is suddenly removed from the output . the energy stored in the inductor rush es into the capacitor, which cause s the output to overshoot. the output capacitance required to meet t he overshoot requirement can be calculated using the following equation: ( ) 2 2 _ 2 _ out ovout out step ov ovout v vv lik c ? ?+ ? = where: k ov is a factor , typically, of 2. v out_ov is the allowable ov ershoot on the output voltage. the output ripple is determined by the esr and the capaci - tance. use the following equation to select a capacitor that can meet the output ripple requirements: ripple out sw l ripple out vf i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ w here: v out_ ripple is the allowable output ripple voltage. r esr is the equivalent series resistance of the output capacitor . select the largest output capacitance given by c out_uv , c out_ov , and c out_ ripple to meet both load transient and output ripple performance. the selected output capacitor voltage rating should be greate r than the output voltage. the rms current rating of the output capacitor should be larger than the result of the following equation: 12 _ l rms c i i out ? = low- side power device se lection the adp2380 has an integrated low - side mosfet driver that drives the low - side nfet. the selection of the low - side nfet affects the dc - to - dc regulator performance. the selected mosfet must meet the following requirements: ? drain -so urce voltage (vds) must be great er than 1.2 vin. ? drain current (id) must be greater than 1.2 i limit_max , which is the selected maximum current - limit threshold. ? the adp2380 low - side gate drive voltage is 8 v. en sure that the selected mosfet can fully turn on at 8 v. total gate charge ( qg at 8 v) must be less than 50 nc. lower qg characteristics constitute higher efficiency. ? the low - side mosfet carries the induc tor current when the high - side mosfet is turned off. for low duty cycle application s , the low - side mosfet carries the output current during most of the period. to achieve higher efficiency, it is important to select a low on -resistance mosfet. the power co nduction loss of the low - side mosfet can be calculated by using the following equation : p fet_low = i out 2 r dson ( 1 C d) where r dson is the on resistance of the low - side mosfet. ? make sure that the mosfet can handle the thermal dissipation due to the powe r loss. some recommended mosfets are listed in table 8 . table 8 . recommended m os fets vendor part no. v ds (v) i d (a) r dson (m?) q g (nc) fairchild fds6298 30 13 12 10 fairchild fds8880 30 10.7 12 12 fairchild fdm s 7578 25 17 8 8 vishay sia430dj 20 10.8 18.5 5.3 aos aon7402 30 39 15 7.1 aos ao4884l 40 10 16 13.6
adp2380 data sheet rev. 0 | page 18 of 28 programming input vo ltage uvlo th e internal voltage divider fro m pvin to gnd sets the default start/stop value s of the input voltage to achieve undervoltage lockout (uvlo) performance. the default rising/falling threshold of pvin and uvlo are listed in table 9 . for a more accurate, externally adjustable uvlo, t hese default values can be replaced by using an external voltage divider , as shown in figure 32. lower values of the external resistors are recommended to obtain a high accuracy uvlo threshold because the values of the internal 320 k? and 125 k? resistors may vary by as much as 20%. table 9. default rising / falling voltage threshold pin rising threshold (v) falling threshold (v) pvin 4.28 3.92 uvlo 1.2 1.1 pvin v in r1 r2 uvlo 320k? 125k? adp2380 09939-032 figure 32 . external programmable uvlo a 1 k? resistor is an appropriate choice for r2 . use the f ollowing e quation to obtain the value of r1 for a chosen input voltage rising threshold: v2.1 v2.1 _ r2 v r1 rising in u w here v in_rising is the rising threshold of v in . the falling threshold of v in can be determined by v1.1 v1.1 _ u r2 r1 v falling in w here v in_falling is the falling threshold of v in . compensation design the adp2380 uses a peak current mode control architecture for excellent load and line trans ient response. for peak current mode control, the power stage can be simplified as a voltage controlled current source , supplying current to the out put capacitor and load resistor. it consists of one domain pole and one zero contributed by the output capacitor esr. the control to output transfer fun ction is given by p z vi comp out vd f s f s ra sv sv sg uu ? ? 1 ? uu uu s s 2 1 2 1 )( )( )( out esr z cr f uuu s 2 1 out esr p crr f uuu )(2 1 s w here: a vi = 8.7 a/v . r is the load resistance . c out is the output capacitance . r esr is the equivalent series resistance of the output capacitor . the external voltage loop is compensated by a transconductance amplifier with a simple external rc net work placed either between comp and gnd or between comp and fb, as shown in figure 33 and figure 34 , respectively . compensation network between comp and gnd figure 33 shows the simplified peak current mode control , small signal circuit with a compensation network placed between comp and gnd. r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out adp2380 gnd comp fb 09939-033 figure 33 . small s ignal c ircuit with compensation n etwork b etween comp and gnd the r c and c c compensation co mponents contribute a zero , and the optional c cp and r c contribute an optional pole. the close d- loop transfer function is as follows : )( 1 1 )( sg s cc ccr s scr cc g rr r st vd cpc cpcc cc cpc m top bot bot v u ? ? 1 ? u uu u uu u u
data sheet adp2380 rev. 0 | page 19 of 28 use t he following design guidelines to select the r c , c c , and c cp compensation components : ? determ ine the cross frequency , f c . generally, fc is between f sw /12 and f sw /6. ? r c can be calculated by vi m ref c out out c agv fcv r = 2 w here: v ref = 0.6 v. g m = 470 s. ? place the compensation zero at the domain pole , f p . c c can be determined by c out esr c r crr c + = )( ? c cp is optional , and it can be used to cancel the zero caused by the esr of the output capacitors. c out esr cp r cr c = compensation network between comp and fb the compensation rc network can also be placed between comp and fb , as shown in figure 34. r esr r + ? g m c out r top r bot ? + a vi v out v comp v out adp2380 gnd comp fb c cp_ea r c_ea c c_ea 09939-034 figure 34 . small s ignal c ircuit with compensation n etwork b etween comp and fb when connecting the compensation network as shown in figure 34 , it requires the same pole and zero as in figure 33 to maintain the same compensation performance. assuming that the compensation networks of figure 33 and figure 34 have the same pole and zero, )1 )(//)( ( ) ( )( )1 )(// ( _ _ __ _ _ _ __ _ __ _ _ __ 0m bot top ea c ea cp ea c ea c ea c ea cp0 ccccp0 0m bot top ea cp ea c ea c ea cp ea c ea c0cpcc0 m ea c ea cp ea c ea ccc rgrrcc crccr crccr rgrrccr ccrrccrr g cc crcr + + + ++ =++ + + = + ? = where: r 0 is the equivalen t output impedance of the trans conductance amplifier, 40 m?. bot top bot top bot top rr rr rr + = // solve the preceding equations to obtain ) )( ( ) )( ( _ _ _ _ arcrb ccrr c c crb r arcrb ccrr gbc 0cc cpcc0 ea cp ea c cc ea c 0cc cpcc0 m ea c + + = + = + + ?= where: )(1 )( )1 )(// ( 0 m ccp0 0m bot top rag ccr b rgrra ++ + = + = adi sim power design tool the adp2380 is sup ported by the adisimpower? design tool set. adisimpower is a collection of tools that produce complete power designs that are optimized for a specific design goal. the tools enable the user to generate a full schematic and bill of materials and calculate p erformance in minutes. adisimpower can optimize designs for cost, area, efficiency, and parts count, while taking into consideration the operating conditions and limitations of the ic and all real external components. for more information about the adisimp ower design tools, visit www.analog.com/adisimpower . the tool set is available from this website, and users can request an unpopulated board.
adp2380 data sheet rev. 0 | page 20 of 28 design example this section provides the procedures for sele cting the external components based on the example specifications listed in table 10 . the schematic of this design example is shown in figure 36 . table 10 . step - down dc -to - dc r egulator requirements parameter specification input voltage v in = 12.0 v 10% output voltage v out = 3.3 v output current i out = 4 a output voltage ripple ?v out_ripple = 33 mv load transient 5%, 1 a to 4 a, 2 a/s switching frequency f sw = 500 khz output voltage setti ng choose a 10 k? resistor as the top feedback resistor (r top ) and calculate the bottom feedback resistor (r bot ). ? ? ? ? ? ? ? ? ? = 6.0 6.0 out top bot v rr to set the output voltage to 3.3 v, the resistors values are r top = 10 k?, r bot = 2.21 k? . frequen cy setting connect a 100 k? resistor from the rt pin to gnd to set the switching frequency at 500 khz. inductor selection the peak - to - peak inductor ripple current, ?i l , is set to 30% of the maximum output current. use the following equation to estimate the inductor value: swl out in fi dvv l ? ? = ) ( where: v in = 12 v. v out = 3.3 v. d = v out /v in = 0.275 . ? i l = 1. 2a. f sw = 500 khz . this results in l = 3.987 h. choose the standard inductor value of 4.7 h. calculate t he peak - to - peak inductor ripple current using t he following equation: ( ) sw out in l fl dvv i ? =? this results in ?i l = 1.02 a. calculate the peak inductor current using the following equation: 2 l out peak i ii ? += this results in i peak = 4.51 a. calculate t he rms current flowing through the inductor usi ng the following equation: 12 2 2 l out rms i ii ? += this results in i rms = 4.01 a. according to the calculated rms and peak inductor current values, select an inductor with a minimum rms current rating of 4.01 a and a minimum saturation current rating of 4.51 a. to protect the inductor from reaching its saturation limit, the inductor should be rated for at least a 7 a saturation current for reliable operation. based on these requirements, select a 4.7 h inductor, such as the fdve1040 - 4r7m from toko, which has a 13.8 m? dcr and an 8.2 a saturation current. output capacitor sel ection the output capacitor is required to meet both the output voltage ripple requirement a nd the load transient response. to meet the output voltage ripple requirement, use the following equation to calculate the esr and capacitance of the output capacitor: ripple out sw l ripple out vf i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ this results in c out_ripple = 7.7 f and r esr = 32 m?. to meet the 5% overshoot and undershoot transient requirements, use the following equations to calculate the capacitance: uvout out in step uv uvout out ovout out step ov ovout vvv lik c v vv lik c _ 2 _ 2 2 _ 2 _ ) (2 ) ( ?? ? = ? ?+ ? = where: k ov = k uv = 2, the coefficients for estimation purpose s. ? i step = 3 a, the load transient step. ? v out_ov = 5%v out , the overshoot voltage. ? v out_uv = 5%v out , the undershoot voltage. this results in c out_ov = 76 f and c out_uv = 30 f. according to the preceding calculation, the output capacitance must be larger than 76 f , and the esr of the out put capaci tor must be smaller than 32 m?. it is recommended that two pieces of 47 f/x5r/6.3 v ceramic capacitors be used, such as the grm32er60j476me20 from m urata , with an esr of 2 m?.
data sheet adp2380 rev. 0 | page 21 of 28 low- side mosfet selectio n a low r dson n-c hannel mosfet is chosen as a high efficiency solution. the breakdown voltage of the mosfet must be higher than 1.2 v in , and the drain current must be larger than 1.2 i limit . it is recommended to use a 30 v, n -c hannel mosfet, such as the fds 6298 from fairchild. the r dson of the fd s 6298 at a 4.5 v driver voltage is 9.4 m?, and the total gate charge at 5 v is 10 nc. compensation compone nts for better load transient and stability performance, set the cross frequency , f c , at f sw /10. in this case, f c = 1/500 khz = 50 khz. ) )( ( ) )( ( _ _ _ 0 _ arcrb ccrr c c crb r arcrb ccrr gbc 0cc cpcc0 ea cp ea c cc ea c 0cc cpcc m ea c + + = + = + + ?= where: r c = vi m ref c out out agv fcv 2 = a/v 7.8 s 470v6.0 khz50 f 322v3.32 = 27.1 k? c c = ( ) c out esr r crr + = k 1.27 f 322)002.0a4 v/ 3.3( ?+ = 1.96 nf c cp = k 1.27 f 322002.0 ? = c out esr r cr = 4.73 pf a = ( ) k 21.2k 10 k 21.2k 10 1 + =+ + 0m bot top bot top rg rr rr (1 + 470 s 40 m?) = 3.4 10 7 b = m 40104.3( s 4701 nf)96.1pf73.4(m 40 )(1 )( 7 ++ + = ++ + 0 m c cp0 rag ccr = 2.26 10 ?6 thi s result s in the following: r c_ea = 52.3 k? . c c_ea = 1055 pf . c cp_ea = 2.45 pf . choose the standard values for r c_ea = 49.9 k?, c c_ea = 1000 p f, and c cp_ea = 2.2 p f. figure 35 shows the b ode plot at 4 a. the cross frequency is 43 khz , and the phase margin is 59. 60 48 36 24 12 0 ?60 ?48 ?36 ?24 ?12 180 144 108 72 36 0 ?180 ?144 ?108 ?72 ?36 1k 10k 100k 1m magnitude (db) phase (db) frequency (hz) 09939-035 figure 35 . bode plot at 4 a soft start time prog ram the soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during soft start and limiting the inrush current. set the soft start time to 4 ms. c ss = v6.0 a 2.3 ms 4 v6.0 _ _ = up ss ext ss it = 21.3 nf choose a standard component value , c ss = 22 n f. input capacitor sele ction a minimum 10 f ceramic capacitor must be placed near the pvin pin. in this application, one 10 f, x5r, 25 v ceramic capacitor is recommended. adp2380 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r top n? 1% r bot n? 1% c ss 22nf r osc n? c in 10f 25v c out1 47f 6.3v c out2 47f 6.3v v out = 3.3v c bst 0.1f c vreg 1f l1 4.7h v in = 12v c c_ea 1000pf c cp_ea 2.2pf r c_ea n? m1 fds6298 09939-036 figure 36 . design example schematic
adp2380 data sheet rev. 0 | page 22 of 28 recommended external components table 11. recommended external components for typical applicat ions with compensation network b etween comp and gnd pins , 4 a output current f sw (khz) v in (v) v out (v) l (h) c out (f) 1 r top (k?) r bot (k?) r c (k?) c c (pf) c cp (pf) 250 12 1 3.3 680 + 2 100 10 15 47 3900 150 12 1.2 3.3 680 10 10 47 3900 100 12 1.5 4.7 680 15 10 60.4 3900 100 12 1.8 4.7 470 20 10 51 3900 100 12 2.5 6.8 3 100 47.5 15 28 3900 10 12 3.3 6.8 2 100 10 2.21 24 3900 10 12 5 10 100 + 47 22 3 29.4 3900 6.8 5 1 3.3 680 + 2 100 10 15 47 3900 150 5 1.2 3.3 680 10 10 47 3900 100 5 1.5 3.3 470 15 10 39 3900 100 5 1.8 3.3 3 100 20 10 20 3900 15 5 2.5 4.7 2 100 47.5 15 18.2 3900 10 5 3.3 3.3 2 100 10 2.21 24 3900 10 500 12 1.2 2.2 470 10 10 68 2200 68 12 1 .5 2.2 3 100 15 10 33 2200 10 12 1.8 2.2 2 100 20 10 26.7 2200 10 12 2.5 3.3 2 100 47.5 15 37.4 2200 6.8 12 3.3 4.7 2 100 10 2.21 47 2200 4.7 12 5 4.7 100 22 3 37.4 2200 3.3 5 1 1.5 470 10 15 56 2200 68 5 1.2 1.5 3 100 10 10 26.7 2200 10 5 1.5 2.2 3 100 15 10 33 2200 10 5 1.8 2.2 2 100 20 10 26.7 2200 10 5 2.5 2.2 2 47 47.5 15 21 2200 6.8 5 3.3 2.2 100 + 47 10 2.21 37.4 2200 4.7 1000 12 1.8 1.5 2 100 20 10 51 1000 4.7 12 2.5 1.5 100 47.5 15 37.4 1000 3.3 12 3.3 2.2 100 10 2.21 47 1000 2.2 12 5 2.2 100 22 3 69 1000 1 5 1 1 3 100 10 15 43.2 1000 8.2 5 1.2 1 2 100 10 10 33 1000 6.8 5 1.5 1 100 + 47 15 10 33 1000 4.7 5 1.8 1 2 47 20 10 30 1000 4.7 5 2.5 1 100 47.5 15 37.4 1000 3.3 5 3.3 1 100 10 2.21 47 1000 2.2 1 680 f: 4 v, sanyo 4tpf680m; 470 f: 6.3 v, sanyo 6tpf470m; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476m e20.
data sheet adp2380 rev. 0 | page 23 of 28 table 12 . recommended external components for typical applicat ions with compensation network b etween comp and fb pins , 4 a output current f sw (khz) v in (v) v out (v) l (h) c out (f) 1 r top (k?) r bot (k?) r c_ea (k?) c c_ea (pf) c cp_ea (pf) 250 12 1 3.3 680 + 2 100 10 15 191 1000 47 12 1.2 3.3 680 10 10 169 1200 33 12 1.5 4.7 680 15 10 237 1000 22 12 1.8 4.7 470 20 10 220 1000 22 12 2.5 6.8 3 100 47.5 15 187 680 1 12 3.3 6.8 2 100 10 2.21 47 2200 4.7 12 5 10 100 + 47 22 3 69.8 1800 2.2 5 1 3.3 680 + 2 100 10 15 191 1000 39 5 1.2 3.3 680 10 10 169 1200 39 5 1.5 3.3 470 15 10 169 1000 22 5 1.8 3.3 3 100 20 10 88.7 1000 3.9 5 2.5 4.7 2 100 47.5 15 124 680 2.2 5 3.3 3.3 2 100 10 2.21 47 2200 15 500 12 1.2 2.2 470 10 10 237 680 22 12 1.5 2.2 3 100 15 10 130 470 2.2 12 1.8 2.2 2 100 20 10 110 470 2.2 12 2.5 3.3 2 100 47.5 15 249 330 1 12 3.3 4.7 2 100 10 2.21 95.3 1000 2.2 12 5 4.7 100 22 3 8 6.6 820 1 5 1 1.5 470 10 15 220 470 22 5 1.2 1.5 3 100 10 10 95.3 680 3.3 5 1.5 2.2 3 100 15 10 130 470 2.2 5 1.8 2.2 2 100 20 10 110 470 2.2 5 2.5 2.2 2 47 47.5 15 147 330 1 5 3.3 2.2 100 + 47 10 2.21 75 1000 1 1000 12 1.8 1.5 2 100 20 10 232 220 1 12 2.5 1.5 100 47.5 15 232 150 1 12 3.3 2.2 100 10 2.21 95.3 470 1 12 5 2.2 100 22 3 169 470 1 5 1 1 3 100 10 15 180 270 2.2 5 1.2 1 2 100 10 10 127 330 2.2 5 1.5 1 100 + 47 15 10 140 270 1 5 1.8 1 2 47 20 10 137 270 1 5 2.5 1 100 47.5 15 249 150 1 5 3.3 1 100 10 2.21 93.1 470 1 1 680 f: 4v, sanyo 4tpf680m; 470 f: 6.3 v, sanyo 6tpf470m; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476me20.
adp2380 data sheet rev. 0 | page 24 of 28 circuit board layout recommendations good circuit board layout is essential for obtaining the best performance from the adp2380 . poor print ed circuit board (pcb) layout degrades the output regulation as well as the electromag netic interface (emi) and electromagnetic compatibility (emc) performance. figure 38 show s a pcb layout example . for optimum layout, use the following guidelines: ? use separate analog ground and power ground planes. connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. in addition, co nnect the ground reference of power components, such as input and output capacitors and a low - side mosfet, to power ground. connect both ground planes to the exposed pad of the adp2380 . ? place the input capacitor, inductor, low - side mosfet, and output capacitor as close to the ic as possible , and use short traces. ? ensure that the high current loop traces are as short and as wide as possible. make the high current pa th from the input capacitor through the inductor, the output capacitor , and the power ground plane back to the input capacitor as short as possible. to accomplish this, ensure that the input and output capacitors share a common power ground plane. in add ition, ensure that the high current path from the power ground plane through the external mosfet, inductor , and output capacitor back to the power ground plane is as short as possible by tying the mosfet source node to the pgnd plane as close as possible t o the input and output capacitors. ? make the low - side driver path from the ld pin of the adp2380 to the external mosfet gate node and back to the pgnd pin of the adp2380 as short as possible , and use a wide trace for better noise immunity. ? connect the exposed pad of the adp2380 to a large copper plane to maximize its power dissipation capability for better thermal dissipation. ? place the feedback resistor divider network as close as possible to the fb pin to prevent noise pickup. try to minimize the length of the trace that connects the top of the feedback resistor divider to the output while keeping the trace away from the high current traces and the switching node to avoid noise pickup. to further reduce noise pickup, place an analo g ground plane on either side of the fb trace and ensure that the trace is as short as possible to reduce parasitic capacitance pickup. adp2380 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r osc r top r bot c ss c in c out v out c bst c vreg l v in c c_ea c cp_ea r c_ea fet 09939-037 figure 37 . high current path in the pcb circuit
data sheet adp2380 rev. 0 | page 25 of 28 pvin pvin uvlo pgood rt sync en/ss comp bst sw sw ld vreg pgnd gnd fb sw pull up power ground plane v out v in input bulk cap input bypass cap analog ground plane r osc c ss inductor low-side mosfet output capacitor r bot r top r c_ea c cp_ea c c_ea c vreg c bst bottom layer trace via copper plane 09939-038 + figure 38 . reco mmended pcb layout
adp2380 data sheet rev. 0 | page 26 of 28 typical application s circuits 09939-039 adp2380 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r top 10k? 1% r bot 10k? 1% c ss 22nf c in 10f 25v c out 470f 6.3v v out = 1.2v c bst 0.1f c vreg 1f l1 2.2h v in = 12v c cp 68pf c c 2.2nf r c 68k? m1 fds6298 r osc 100k? figure 39 . compensation network between comp and gnd, v in = 12 v, v out = 1.2 v, i out = 4 a, f sw = 500 khz 09939-040 adp2380 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r top 20k? 1% r bot 10k? 1% c ss 22nf c in 10f 25v c out1 100f 6.3v c out2 100f 6.3v v out = 1.8v c bst 0.1f c vreg 1f l1 2.2h v in = 12v c c_ea 470pf c cp_ea 2.2pf r c_ea 110k? m1 fds6298 r1 7.32k? 1% r2 1k? 1% r osc 100k? figure 40 . programming input voltage uvlo r ising threshold at 10 v, v in = 12 v, v out = 1.8 v, i out = 4 a, f sw = 500 khz 09939-041 adp2380 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r osc 82k? r top 22k? 1% r sot 3k? 1% c in 10f 25v c out 100f 6.3v v out = 5v c bst 0.1f c vreg 1f l1 4.7h v in = 12v c c_ea 820pf c cp_ea 1pf r c_ea 100k? m1 fds6298 figure 41 . using internal soft start , programming switching frequency at 600 khz, v in = 12 v, v out = 5 v, i out = 4 a, f sw = 600 khz
data sheet adp2380 rev. 0 | page 27 of 28 outline dime nsions compliant to jedec standards mo-153-abt 08-03-2010-a 16 9 8 1 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bottom view top view 9 16 1 8 pin 1 indicator 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 2.31 1.75 2.46 1.75 exposed pad 1.10 max seating plane 0.15 max 0.05 min coplanarity 0.076 0.95 0.90 0.85 0.30 0.19 0.65 bsc 0.20 0.09 0.25 8 0 0.70 0.60 0.50 figure 42 . 16 - lead thin shrink small outline with exposed pad [tssop_ep] (re - 16 - 3) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adp2380arez - r7 ?40c to +125c 16- lead tssop_ep, 7 tape and reel re -16 -3 adp2380arez ?40c to +125c 16 - lead tssop_ep, tube re - 16 - 3 adp2380 - evalz evaluation board 1 z = rohs compliant part.
adp2380 data sheet rev. 0 | page 28 of 28 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09939 -0- 12/12(0)

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